The present invention relates generally to semiconductor structures and semiconductor device processing and, more particularly, to a method for implementing self-aligned, deep trench shaping for vertical DRAM devices.
Dynamic random access memory (DRAM) is a type of semiconductor memory in which the information is stored as data bits in capacitors on a semiconductor integrated circuit. Each bit is typically stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. A practical DRAM circuit usually includes an array ray of memory cells interconnected by rows and columns, which are generally referred to as wordlines and bitlines, respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bit-lines. More specifically, a trench DRAM memory cell may include a metal-oxide-semiconductor field-effect transistor (MOSFET) connected to a deep trench (DT) capacitor. The transistor includes gate and diffusion regions that are referred to as either drain or source regions, depending on the operation of the transistor.
Typically, the deep trench capacitor is formed in a silicon substrate using one or more conventional techniques, such as reactive ion etching (RIE), with photoresist or other materials as a mask to cover the areas where trench formation is not desired. The trench is typically filled with a conductor material (most commonly n-type doped polysilicon), which serves as one plate of the capacitor, usually referred to as the “storage node”. The second plate of the capacitor is typically formed by outdiffusion of an n-type doped region surrounding the lower portion of the trench, usually referred to as the “buried plate”. A node dielectric layer, which may include, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or any other dielectric material, is provided to separate the storage node and buried plate, thereby forming the capacitor. The connection between the transistor and the capacitor is achieved through the formation of what is known in the art as a “buried strap”, which is commonly formed by outdiffusion of dopants from the doped polysilicon to the substrate.
Compared to a planar DRAM device, which includes a planar transfer device and a storage node in a trench, a vertical DRAM device exploits a trench to form both the storage node and the transfer device. Such vertical DRAM devices have significant advantages. For example, the memory density is increased because the length of the vertical signal transfer device channel is determined by a recess process, and therefore it is decoupled from the minimum feature size which is limited by the capability of the lithography. The vertical configuration also allows longer channel lengths without a proportional decrease in memory density. Channel length can also be properly scaled relative to gate oxide thickness and relative to junction depth to reduce channel doping, minimize junction leakage, and increase retention times.
In order to prevent carriers from traveling through the substrate between the adjacent devices (e.g., capacitors), device isolation regions are formed between adjacent semiconductor devices. Trench isolation (IT) is generally used in the fabrication of advanced semiconductor devices. A sharply defined trench is formed in the semiconductor substrate, and the trench is thereafter filled with oxide back to the surface of the substrate to provide a device isolation region. The remaining surfaces of the substrate without IT are generally referred to as the active area (AA).
During the formation of the deep trenches, the actual resulting shape of the deep trenches is not geometrically rectangular at the upper trench portion due to the crystalline orientation dependence of the etch rate in a reactive ion etch (RIE) process. Rather, the upper portion of the etched deep trench takes on an octagonal configuration. In addition, because of process variations that occur during device processing, perfect alignment of the active areas (AA) to the deep trenches is not always achieved. As a result, the combination of a non-rectangular shaped deep trench and an AA-DT misalignment can cause a variation of the device threshold voltage (Vt) and consequently degrades the DRAM device performance.